Nowadays quantum-dot cellular automata has been playing a major challenge in competition of developing molecular circuits which overcomes certain fatal complications of CMOS devices for instance impurity inconsistency, high device latency etc. Quantum-dot cellular automata empires the quantum binary logic gate designing technology by the help of fastest quantum bits. The electronic orientation assigns the binary q-bits inside the q-cells. In this letter one novel methodology for tunneling barrier resistivity analysis and device latency calculation have proposed. The tunneling barrier resistivity has propounded with a generalized mathematical expression to reveal the instantaneous effect of barrier resistance to the electron during tunneling. Proposed technique for switching time computation explores the signal propagation delay by considering the directional flow of quantum signals through different cells under different clock zones. Furthermore, in this letter one novel cell wise energy and power dissipation computation technique has proposed which offers a very accurate power drop data for the QCA wires. The proposed mathematical expressions are flexible enough for computing the power drop for any homoaxial wire and for any off centered or heteroaxial wire. This contribution extends a previous work on switching time, provided in reference.