First Workshop on Pioneering Processor Paradigms(Wp3 2017)

Austin, TX, USA

February 04, 2017

Call for Papers :

The workshop on pioneering processor paradigms invites survey (or tutorial)-like submissions for review. The ideal paper would highlight a single pioneering paper (or set of papers) constituting a major processing, design, modeling or software paradigm shift in the past. In addition to explaining the context and basic concepts articulated in such work, the author(s) should draw relevant conclusions about how this pioneering work could or should influence computing paradigms of the future.

Topics of Interest

• Processing and cache taxonomy papers.
• RISC architectures and CISC-to-RISC dynamic translation support.
• Processor pipelining, super scalar processing and branch prediction innovations.
• Register renaming, out-of-order execution and precise interruption.
• Cycle-accurate processor performance modeling.
• Innovations in floating point arithmetic units and vector/SIMD acceleration.
• VLIW architectures.
• Multi-threading, multiscalar and speculative multi-threading.
• Homogeneous and heterogeneous multi-core processors; accelerator-enabled efficiency boost.
• Power, temperature, and reliability-aware computing – with associated modeling innovations.
• Compiler innovations in support of novel microarchitectural paradigms.
• Circuit design innovations in support of (micro)-architectural paradigm shifts.
  

IMPORTANT DATES

• Submission deadline: December 4, 2016
• Notification of acceptance: December 18, 2016
• Final paper submission: January 8, 2017
• Workshop date: February 4, 2017

User Name : jerish
Posted 30-11-2016 on 09:40:28 AEDT

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