International Workshop Advancements in Parallel Programming Models and Frameworks for the Multi-/Many-core Era ( APPM 2017 )
Jul 17, 2017 - Jul 21, 2017, Genoa, Italy

With multi- and many-core based systems, performance increase on the microprocessor side will continue according to Moore's Law, at least in the near future.  However, the already existing performance limitations due to slow memory access are expected to get worse with multiple cores on a chip, and complex hierarchies of cache memory will make it hard for users to fully exploit the theoretically available performance.  In addition, the increasingly hybrid and hierarchical design of compute clusters and high-end supercomputers, as well as the use of accelerator components (GPGPUs by AMD and NVIDIA, Intel Xeon Phi, Intel SCC, integrated GPUs etc.) add further challenges to efficient programming in HPC applications. 

Therefore, compute and data intensive tasks can only benefit from the hardware's full potential, if both processor and architecture features are taken into account at all stages - from the early algorithmic design, via appropriate programming models, up to the final implementation.