Untitled Document
International Workshop on High Performance Dynamic Reconfigurable Systems and Networks
(DRSN 2017)
July 17-21, 2017, Genoa, Italy
Call for Papers:
Reconfigurable Systems (RS) and Networks on Chips (NoC) are increasingly finding use in applications that require high-performance computing (HPC), power-efficiency, or both. Field-Programmable Gate Arrays (FPGAs) are seeing adoption in mainstream for both big-data and big-compute applications. The use of NoCs - as opposed to conventional bus-based communication architectures - is already established in a variety of architectures.
While there is considerable maturity in the area of NoC and RS architectures, there is that familiar gap between the capability of such architectures, and the capability of programmers, compilers, and runtime systems to efficiently exploit the performance and efficiency dividends these architectures promise.
Topics:
- Jürgen Becker, Karlsruhe Institute of Technology (KIT), Germany
- Sven Hartmann, TU Clausthal, Germany
- Falco Bapp, Karlsruhe Institute of Technology (KIT), Germany
- Masoud Daneshtalab, KTH Royal Institute of Technology, Sweden
- Umut Durak, German Aerospace Center (DLR), Germany
- Miriam Leeser, Northeastern University, Massachusetts, USA
- Jari Nurmi, Tampere University of Technology, Finland
- Thilo Pionteck, University of Lübeck, Germany
- Sai Rahul Chalamalasetti, Hewlett-Packard Labs, California, USA
- Andreas Reinhardt, TU Clausthal, Germany
- Dirk Stroobandt, Ghent University, Belgium
- Zain Ul-Abdin, Halmstad University, Sweden
- Nikos Voros, Technological Educational Institute of Western Greece (TWG), Greece
- Syed Waqar Nabi, University of Glasgow, U.K.
- Muhammad Adeel Pasha, LUMS
- Aaron Smith, Research
- TBA
Important Dates:
- Workshop/Tutorial Proposal deadline:Mar 27, 2017
- Notification of Acceptance:Apr 15, 2017
- Final Version Due:May 03, 2017
User Name : scott
Posted 20-03-2017 on 19:11:45 AEDT
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