ASIC Implementation of I2C Master bus controller with design of Firm IP core has been proposed in this paper. I2C is one the most prominent protocol used in on chip communication among sub-systems. The generic design of I2C master controller has ample of features to incorporate vast varieties of application and I2C standards. The generic design is slow, congested and require high power. It’s rare to utilize all the features of generic design fully in a single particular application or system. Hence, a modified ASIC design with specific less features but with better timing, low power requirement and less area overhead, has been proposed in this paper. This design is specifically apt for digital systems which have serial bus interface requirement for on board communication. Moreover, the Firm IP core of I2C Master Controller has been designed for ASIC, which makes the design highly portable on any ASIC chips or SOC designs. The firm IPs is best in terms of flexibility and more predictable than commonly found soft IPs. The entire custom ASIC implementation of proposed design has been done in Cadence Tool chain with 45nm technology using standard cell library. A thorough comparison has been done between generic open sourced RTL design of I2C Controller obtained from Opencores.org and our proposed design