Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effect Transistors in 32 Nanometer Technology
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Author : Ali Ghorbani and Ghazaleh Ghorbani
Affiliation : Islamic Azad University
Country : Iran
Category : Electronics Engineering
Volume, Issue, Month, Year : 5, 5, October, 2014
Abstract :
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs). Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer technology in Different values of temperature and VDD.
Keyword : Low power circuit; Carbon Nanotube Filed Effect Transistors; Nano Transistors; Full Adder
URL : https://aircconline.com/vlsics/V5N5/5514vlsi01.pdf
User Name : Ryan cooper
Posted 21-11-2024 on 21:51:28 AEDT
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