Power consumption reduction is transpiring drift in area of VLSI digital signal processing. This gives rise to need of minimization of silicon area which is done by folding algorithm. As silicon area decreases power consumption of a circuit decreases. Folding is an algorithm which reduces silicon chip area by combining various arithmetic operations into one operation by time scheduling technique. It is applied on iterative data flow graph with appropriate folding set. Least mean square algorithm alters coefficients of Adaptive filter in order to achieve desired output. Proposed work is focused on design of efficient VLSI architecture for LMS adaptive filter aims at reducing mainly area which results in power consumption reduction and hardware complexity. LMS filter structure used here is called non-canonical as transpose FIR structure is used. Results show that numbers of adders are reduced by 37.5 % and multipliers by 33.33% without changing characteristics of filter.