This paper presents a low power, high gain, low area low pass filter design. The pre-processing block in this filter is the two-stage operational amplifier which is designed using the DTMOSFETS. This filter is operated at very low supply voltages of +0.2V.The PMOS input differential pairs are used to enhance the driving capability of the op-amp. input stage of the op-amp is the differential amplifier in which the inputs are provided to the two PMOS transistors. The second stage is the gain stage in which common source amplifier is used. The design parameter values are determined which optimize an objective feature satisfying specifications or constraints. The low pass filter is designed with a cut-off frequency of 100-HZ and a resistance of 10ohms, which occupies more layout area. In order to reduce the layout area the low pass filter is designed using the switched capacitor. The circuit is implemented with a supply voltage of 0.4V in 0.9-um technology, with a power consumptio