REDUCED COMPLEXITY QUASI-CYCLIC LDPC ENCODER FOR IEEE 802.11N
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Author : Monica Mankar , Gajendra Asutkar , Pravin Dakhole
Affiliation : Research Scholar Department of Electronics Engineering , Yeshwantrao Chavan college of Engineering., Nagpur, India.
Country : India
Category : Digital Signal & Image Processing
Volume, Issue, Month, Year : Vol 7, No 5/6, December, 2016
Abstract :
In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder
hardware based on Richardson and Urbanke lower- triangular algorithm for IEEE 802.11n wireless LAN
Standard for 648 block length and 1/2 code rate. The LDPC encoder hardware implementation works at
301.433MHz and it can process 12.12 Gbps throughput. We apply the concept of multiplication by
constant matrices in GF(2) due to which hardware required is also optimized. Proposed architecture of
QC-LDPC encoder will be compatible for high-speed applications. This hardwired architecture is less
complex as it avoids conventionally used block memories and cyclic-shifters.
Keyword : Quasi-cyclic -low-density-parity-check (QC-LDPC), WLAN (IEEE802.11n), Richardson and Urbanke lower- triangular algorithm, encoder
Journal/ Proceedings Name : International Journal of VLSI design & Communication Systems (VLSICS)
URL : http://aircconline.com/vlsics/V7N6/7616vlsi04.pdf
User Name : james
Posted 25-01-2017 on 15:49:35 AEDT
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