VLSI IMPLEMENTATION OF AREA EFFICIENT 2-PARALLEL FIR DIGITAL FILTER
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Author : L kholee phimu and Manoj kumar
Affiliation : Electronic and Communication Engineering, NIT Manipur, India
Country : India
Category : Digital Signal & Image Processing
Volume, Issue, Month, Year : Vol 7, No 5/6, December, 2016
Abstract :
This paper aims to implement an area efficient 2-parallel FIR digital filter. Xilinx 14.2 is used for synthesis
and simulation. Parallel filters are designed by using VHDL. Comparison among primary 2–parallel FIR
digital filter and area efficient 2-parallel FIR digital filter has been done. Since adders are less weight in
term of silicon area, compare to multipliers. Therefore multipliers are replaced with adders for reducing
area and speed of the filter. 2-parallel FIR filter is used in digital signal processing (DSP) application.
Keyword : Finite impulse response (FIR), Booth multiplier, Carry-look-ahead adder (CLA), Digital Signal Processing (DSP), Parallel FIR, Very Large Scale Integration (VLSI).
Journal/ Proceedings Name : International Journal of VLSI design & Communication Systems (VLSICS)
URL : http://aircconline.com/vlsics/V7N6/7616vlsi02.pdf
User Name : babu
Posted 03-01-2017 on 09:47:29 AEDT
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