IEEE/ACM International Symposium on Nanoscale Architectures
(NANOARCH 2017)
25-26 July 2017
NewPort, USA

NANOARCH 2017 is the leading conference on post-CMOS nanocircuits, nanoarchitectures, emerging nanoscale CMOS, and nanoscale fabrics in general. Both experimental and theoretical works are sought after.

NewportNANOARCH is the annual cross-disciplinary forum for the discussion of novel post-CMOS nanocomputing directions and emerging nanoscale CMOS. The symposium seeks papers on innovative ideas for solutions to the principal challenge facing integrated electronics in the 21st century - how to design, fabricate, and integrate nanosystems to overcome the fundamental limitations of CMOS. In particular, such systems could (1) contain unconventional nanodevices with unique capabilities, including directions beyond simple switches, (2) introduce new logic and memory concepts, (3) involve novel circuit styles, (4) introduce new concepts for computing, (5) reconfigure and/or mask faults at much higher rates than in CMOS, (6) explore security architectures with nanotechnology, (7) involve new paradigms for manufacturing, and (8) rethink the methodologies and design tools involved.

Example topics (both theoretical and experimental) of interest include (but are not limited to):

• Novel nanodevices and manufacturing/integration ideas with a focus on nanoarchitectures
  
• Nanoelectronic circuits, nanofabrics, computing paradigms and nanoarchitectures
  
• 2D/3D/hybrid nanodevice integration and manufacturing, with variability, defect and fault tolerance
  
• Nanodevice and nanocircuit models, methodologies and computer aided design tools
  
• Fundamental limits of computing at the nanoscale
  

Important Deadlines:

• Submission Deadline: April 15, 2017
  
• Acceptance Notification: May 15, 2017
  
• Final Version Due: June 7, 2017
  
• Early Registration: June 7, 2017
  
  

User Name : shaun
Posted 25-11-2016 on 13:01:32 AEDT

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