29th IEEE International Conference on VLSI Design(VLSID 2016)

Jan 4-8, 2016

Kolkata, West Bengal, India

Call For Papers

The 29th International Conference on VLSI Design and the 15th International Conference on Embedded Systems will bring together industry and academia to present front-end technology under the theme of "Technologies for a Safe and Inclusive World (TSIW)". The convergence of technology with modern life has reached a state where dependence of human life on semiconductor technology is ubiquitous. Today semiconductor technology is poised to look beyond its traditional bastions of application with pervasive impact on transportation, energy, disaster management, environment, and healthcare. 

Topics

Track : Design Methodology and Technology
• D1: System-level Design

  ESL, System-level design methodology, Multicore systems, Processor and memory design, Concurrent interconnect, Networks-on-chip, Defect tolerant architectures

• D2: Advances in Digital Design

  Logic and Physical synthesis; Place & Route, Clock Tree, Physical Verification, Timing and Signal integrity, Power analysis and integrity, OCV, DFM; DFY; Challenges for advanced technology nodes

• D3: Analog / RF Design

  Analog Mixed Signal IP; High-Speed interfaces; SDR and wireless; Low-power Analog and RF; Effective use of Spectrum; Memory Design, Standard Cell Design

• D4: Power Aware Design

  Low-power design, micro-architectural techniques, thermal estimation and optimization, power estimation methodologies, and CAD tools

• D5: Devices / Circuits

  New Devices and architectures; Low power devices; Modeling and Simulation; Multi-domain simulation; Numerical methods; Device/circuit level variability models; Reliability simulation

• D6: Emerging Technologies

  Nano-CMOS technologies; MEMS; CMOS sensors; CAD/EDA methodologies for nanotechnology; Nano-electronics and Nano-circuits, Nano-sensors, MEMS applications, Nano-assemblies and Devices, Non-classical CMOS; Post-CMOS devices; Biomedical circuits, Carbon Nano-tubes based computing

Track : Design Tools and EDA
• T1: Design Verification

  Functional Verification; Behavioral Simulation; RTL Simulation; Coverage Driven Verification; Assertion Based Verification; Gate-level simulation; Emulation; Hardware Assisted Verification; Formal Verification; Equivalence Checking; Verification Methodologies

• T2: Test Reliability and Fault-Tolerance

  DFT, Fault modelling/simulation; ATPG; Low Power DFT; BIST & Repair; Delay test; Fault tolerance; Online test; AMS/RF test; Board-level and system-level test; Silicon debug, post-silicon validation; Memory test; Reliability test; static and dynamic defect- and fault-recoverability, and variation-aware design

• T3: Computer-Aided Design (CAD)

  Hardware/software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction)

Track : Embedded System Design and Tools
• E1: Embedded Systems

  Hardware/Software co-design & verification; Reconfigurable computing; Embedded multi-cores SOC and systems; Embedded software including Operating Systems, Firmware, Middleware, Communication, Virtualization, Encryption, Compression, Security, Reliability; Hybrid systems-on-chip; Embedded applications, Platforms & Case studies

• E2: FPGA Design and Roconfigurable Systems

  FPGA Architecture, FPGA Circuit Design, CAD for FPGA, FPGA Prototyping

• E3: Wireless Systems

  Wireless Sensor Networks, Low Power wireless Systems, Embedded Wireless, Wireless protocols, Wireless Power / Charging

Theme Track : Technologies for a Safe and Inclusive World
• H1: Technologies for Healthcare Applications

  Security/authentication based on bio-encryption techniques, Low-power ASIC design for biomedical signal processing, Ultra-low-power sensor and bio-interface design, Biomedical signal processing for multi-channel arrays such as orthogonal codes, compressive sensing, Biomedical image processing for different biometrics, Telemedicine for affordable and rural healthcare, Wireless and energy harvesting technology, Smart textiles for biomedical applications, In vivo implantable device.

• H2: Technologies for Smart Management of Energy Systems

  Design, synthesis and verification of smart energy system, Security and privacy for smart energy system, Big data analytics for smart energy system, Cross hardware and software layer modeling and optimization for smart energy system, Fault detection and recovery for smart energy system, Sustainability in smart energy system, Emerging applications including (but not limited to) smart grid, smart building, smart home, smart automobile, etc.

• H3: Technologies for Intelligent and Secure Transportation Systems

  All aspects related to building intelligent and secure transportation systems (Automotive, Aerospace, Railways, etc.) with the emphasis on Design Methodologies, Architecture and Platforms, Validation and Verification, Modeling and Simulation, Safety, Security and Reliability.

• H4: Technologies for Safety Assurance of Embedded Circuits and Systems

  Safety Standards - Interpretation and Adherence, Verification tools and techniques for safety in circuits and systems, Formal methods for safety assurance, Design for safety and robustness, Software and hardware architectures for safe and reliable systems.

• H5: Technologies for Secure Embedded Circuits and Systems

  Efficient cryptographic implementations such as lightweight and secure processors and co-processors, hardware accelerators for public-key protocols, random numbers generators, physical unclonable functions (PUFs); Side-channel and fault attacks against implementations and countermeasures; Hardware Trojan attacks and detection techniques; Secure CAD tools for embedded system design.

IMPORTANT DATES            

Paper submission: Jul 26, 2015

                       

Notification of acceptance:Sep 26, 2015

           

Final manuscripts due:Oct 11, 2015

                       

Conference dates: Jan 4-8,2016

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